A display apparatus, for example, a liquid crystal display apparatus widely is used for various kinds of electronic equipment as a thin and light-weight flat display. In particular, an active matrix type liquid crystal display apparatus using a switching element such as a thin film transistor (TFT) actively is being applied to a monitor display for a personal computer, a liquid crystal TV, and the like due to its excellent image characteristics.
First, the basic configuration of an active matrix type display apparatus will be described with reference to FIG. 3. The display apparatus roughly is composed of a scanning signal driving circuit 21, a video signal driving circuit 22, and a display element 23. The display element includes, as its main components, a plurality of pixel electrodes 5 disposed in a matrix, a plurality of switching elements 3 (generally, a thin film transistor (TFT) or the like is used) arranged corresponding to the pixel electrodes 5, and a plurality of scanning electrodes 1 disposed in a line direction (horizontal direction) and a plurality of video signal electrodes 2 arranged in a column direction (vertical direction) corresponding to the matrix arrangement of the pixel electrodes. The video signal electrodes 2 are connected electrically to the pixel electrodes 5 via the switching elements 3. Furthermore, a counter electrode 20 is provided so as to oppose the pixel electrodes 5, and a display medium such as liquid crystal is inserted between the pixel electrodes 5 and the counter electrodes 20. Furthermore, electrodes called common electrodes 4 are provided in parallel with the scanning electrodes 1, and storage capacitors 7 are provided between the common electrodes 4 and the pixel electrodes 5. The video signal driving circuit 22 supplies a video signal to a plurality of video signal electrodes 2 of the display element 23. Furthermore, the scanning signal driving circuit 21 supplies a scanning signal for controlling conduction of the switching elements 3 to a plurality of scanning electrodes 1 of the display element 23.
JP 5(1993)-143021 discloses a method for driving an active matrix type liquid crystal display apparatus. According to this method, wiring called common electrodes is provided in parallel with scanning electrodes (gate electrodes or gate lines), storage capacitors are formed between the common electrodes and the pixel electrodes, the potential of the common electrodes is varied in synchronization with that of the scanning electrodes, and a superimposed voltage is applied to the potential of the pixel electrodes by capacitive coupling through the storage capacitors. Because of the effect of the superimposition of a voltage, a decrease in a video signal voltage (source voltage), a reduction in driving power, enhancement of response speed and driving reliability, and the like are achieved.
FIG. 14 is an equivalent circuit diagram of one pixel of a liquid crystal display apparatus in which a storage capacitance Cst (Cst is a common electrode-pixel electrode capacitance in more general terms) is formed between a common electrode and a pixel electrode. FIG. 15 is a diagram illustrating the potential of each portion in the case where the liquid crystal display apparatus 1 is driven. In FIG. 14, TFT represents a thin film transistor, Cgd represents a gate-drain capacitance (scanning electrode-pixel electrode capacitance), Clc represents a pixel electrode-counter electrode capacitance (which is a capacitance mainly from liquid crystal; however, there also is a capacitance component generated by electrical addition in series or in parallel from the other medium. Alternatively, such a capacitance may be applied intentionally) formed between a pixel electrode and a counter electrode provided so as to oppose the pixel electrode with liquid crystal interposed therebetween, Vg(n) represents the potential of a scanning electrode, Vs represents the potential of a video signal, Vd represents the potential of a pixel electrode, Vd represents the potential of a counter electrode, and Vc(n) represents the potential of a common electrode. The pixels are arranged in a matrix, and Vg and Vc are provided with a suffix “n” since the n-th pixel is paid attention to.
A plurality of scanning electrodes, pixel electrodes, and the like are arranged in a matrix. For a strict definition, based on a scanning electrode, a pixel (generally, there are a plurality of such pixels) whose ON/OFF (of a TFT) is controlled by the scanning electrode may be referred to as “a pixel belonging to the scanning electrode”. In contrast, based on a pixel (or a pixel electrode), a scanning electrode that controls ON/OFF of a TFT of the pixel may be referred to as “a scanning electrode of the stage concerned”. The pixel electrode (Vd) in FIG. 14 refers to “a pixel electrode belonging to the scanning electrode (Vg(n)), and the scanning electrode (Vg(n)) refers to “a scanning electrode of the stage concerned with respect to the pixel (Vd). Hereinafter, unless otherwise specified, the term “pixel (electrode)” or “scanning electrode” simply will be used.
There also are a plurality of common electrodes. Therefore, in the case of strictly specifying a common electrode, the expression “common electrode that is the other connection destination of storage capacitance connected to a pixel electrode” or the like will be used. The common electrode (Vc(n)) in FIG. 14 refers to “a common electrode that is the other connection destination of storage capacitance connected to the pixel electrode (Vd)”. However, this also will be simply referred to as “a common electrode”.
As shown in FIG. 15, in an odd-numbered frame, a video signal voltage takes a negative value based on Vd (i.e., Vsig(−)). When the potential of a scanning electrode Vg becomes an ON level (first potential level of a scanning electrode) Vgon, a TFT is brought into conduction (ON state), and the potential of a pixel Vd is charged to Vsig(−). At this time, the potential of a common electrode has a value Vc(−) (second potential level of a common electrode). Then, under the condition that Vg(n) is at an OFF level (second potential level of the scanning electrode) Vgoff, the TFT is brought out of conduction (OFF state). Thereafter, when the potential of the common electrode is changed in a downward direction i.e., from Vc(−) to Vcoff (third potential level of the common electrode), the pixel potential Vd is superimposed with a coupling voltage proportional to the voltage difference in a downward direction (arrow in FIG. 15).
In an even-numbered frame, a video signal voltage takes a positive value based on Vd (i.e., Vsig(+)). When a pixel is charged to Vsig(+), the potential of the common electrode is set at Vc(+) (first potential level of the common electrode). After discharging is completed and the potential of the scanning electrode falls, the potential of the common electrode is changed from Vc(+) to Vcoff in an upward direction. The pixel potential Vd is superimposed with a coupling voltage proportional to the voltage difference in an upward direction.
Consequently, while a voltage with a small amplitude (Vsig(+) and Vsig(−)) is applied to a video signal electrode, a pixel electrode can be supplied with a voltage with a larger amplitude (Vdo(+) and Vdo(−)). For example, by using an IC for a video signal of an output voltage range of 5 V, a voltage range applied to liquid crystal can be increased to 10 V or 15 V. Thus, while using an IC with a low withstand voltage, the liquid crystal can be driven with a voltage equal to or higher than the withstand voltage.
A period during which the potential of the common electrode becomes Vc(+) or Vc(−) will be referred to as a common electrode compensating period, and the voltage Vc(±) will be referred to as a common electrode compensating voltage (compensating potential). Although it is desirable that Vc(+) is different from Vc(−), Vcoff may be the same voltage as either Vc(+) or Vc(−). Furthermore, the potential of the common electrode is not always required to be either Vc(+) or Vc(−) while the potential of the scanning electrode is Vgon. The potential of the common electrode should be at this value at least when the scanning electrode falls from Vgon to Vgoff (more specifically, when a TFT is changed from an ON state to an OFF state).
The scanning signal driving circuit has two output levels, and the common electrode potential control circuit has three output levels. More specifically, the scanning signal driving circuit has a first potential level Vgon and a second potential level Vgoff, and the common electrode potential control circuit has a first potential level Vc(+), a second potential level Vc(−), and a third potential level Vcoff. In general, three power sources are required of the common electrode potential driving circuit so as to correspond to the above-mentioned three potential levels. However, if either one of the first potential level Vc(+) or the second potential level Vc(−) is made equal to the third potential level Vcoff, only two power sources are enough. Even in the case where either of the compensating potentials is equal to Vcoff, the potential levels are considered to be different, so that three potential levels are considered to be present.
It is simply that the above-mentioned superimposition of a voltage is conservation of charge on a pixel electrode from a different point of view. More specifically, during a period from a time immediately before charging of a pixel is completed and the potential of a scanning electrode falls (the potential of the scanning electrode is Vgon) to a time when the common electrode compensating period is completed, charge of the pixel electrode is stored. Therefore, in each of the odd-numbered frame and the even-numbered frame, the following (Formula 11) is obtained.                                                         C              gd                        ⁡                          (                                                                    V                    sig                                    ⁡                                      (                    -                    )                                                  -                                  V                  gon                                            )                                +                                    C              st                        ⁡                          (                                                                    V                    sig                                    ⁡                                      (                    -                    )                                                  -                                                      V                    c                                    ⁡                                      (                    -                    )                                                              )                                +                                    C              lc                        ⁡                          (                                                                    V                    sig                                    ⁡                                      (                    -                    )                                                  -                Vd                            )                                      =                                                            C                gd                            ⁡                              (                                                                            V                      do                                        ⁡                                          (                      -                      )                                                        -                                      V                    goff                                                  )                                      +                                          C                st                            ⁡                              (                                                                            V                      do                                        ⁡                                          (                      -                      )                                                        -                                      V                    coff                                                  )                                      +                                                            C                  lc                                ⁡                                  (                                                                                    V                        do                                            ⁡                                              (                        -                        )                                                              -                                          V                      d                                                        )                                            ⁢                                                C                  gd                                ⁡                                  (                                                                                    V                        sig                                            ⁡                                              (                        +                        )                                                              -                                          V                      gon                                                        )                                                      +                                          C                st                            ⁡                              (                                                                            V                      sig                                        ⁡                                          (                      +                      )                                                        -                                                            V                      c                                        ⁡                                          (                      +                      )                                                                      )                                      +                                          C                lc                            ⁡                              (                                                                            V                      sig                                        ⁡                                          (                      +                      )                                                        -                                      V                    d                                                  )                                              =                                                    C                gd                            ⁡                              (                                                                            V                      do                                        ⁡                                          (                      +                      )                                                        -                                      V                    goff                                                  )                                      +                                          C                st                            ⁡                              (                                                                            V                      do                                        ⁡                                          (                      +                      )                                                        -                                      V                    coff                                                  )                                      +                                          C                lc                            ⁡                              (                                                                            V                      do                                        ⁡                                          (                      +                      )                                                        -                                      V                    d                                                  )                                                                        (                  Formula          ⁢                                           ⁢          11                )            
The following (Formulae 12) are obtained by modifying Formula 11.Vdo(−)=Vsig(−)−αstΔVc(−)−αgdΔVgonVdo(+)=Vsig(+)−αstΔVc(+)−αgdΔVgon  (Formula 12)
ΔVgon, ΔVc(+), ΔVc(−), and αgd, αst are represented by the following (Formula 13) and (Formula 14).ΔVgon=Vgon−VgoffΔVc(+)=Vc(+)−VcoffΔVc(−)=Vc(−)−Vcoff  (Formula 13)αgd=Cgd/Ctotαst=Cst/CtotCtot=Cgd+Clc+Cst  (Formula 14)
In both (Formulae 12), the second term of the right side corresponds to a superimposed portion by a (capacitive) coupling voltage from the common electrode, and is determined by ΔVc(+) or ΔVc(−). ΔVc(+) or ΔVc(−) is a value of a potential (in this case, Vc(+) or Vc(−)), at a moment when a pixel is charged, of a common electrode to which storage capacitance is connected, based on the potential (in this case, Vcoff) in a retained state. The third term of the right side of (Formulae 12) is a (capacitive) coupling voltage from a scanning electrode, and is called a feedthrough. Ctot in (Formula 14) can be considered as the total capacitance electrically connected to the pixel electrode.
As described with reference to FIG. 15, the pixel electrode is charged with a signal voltage with its polarity inverted per frame. At this time, it may be possible that the entire screen is set at the same polarity, and the polarity is inverted per frame (field inversion system). In addition, there are a system of inverting the polarity per line (line inversion system), a system of inverting the polarity per column (column inversion system), and a system of inverting the polarity in a checkered pattern by combining the line inversion and the column inversion (dot inversion system). A charging pattern of a pixel by each system is drawn as in FIGS. 16A, 16B, 16C, and 16D. Voltage waveforms applied to video signal electrodes VSP and VSQ adjacent to each other can be drawn as shown on the right side of each figure.
In the case of the field inversion and the column inversion, the polarity of a video signal applied to a video signal electrode in one frame is constant. However, in the case of the line inversion and the dot inversion, the polarity of a video signal is inverted every time each scanning electrode is selected. Furthermore, in the case of the field inversion and the line inversion, the polarity is the same between the adjacent video signal electrodes. However, in the case of the column inversion and the dot inversion, the polarity becomes opposite between the adjacent video signal electrodes. In the case of the column inversion and the dot inversion, the video signal driving circuit has a function of simultaneously applying two kinds (i.e., positive polarity and negative polarity) of video signals having different polarities to a plurality of video signal electrodes.
Among the respective systems, S. Tomita et al. (Journal of the SID, ½ (1993), pp. 211-218) describe in detail that horizontal crosstalk is likely to occur in the field inversion and the line inversion. Hereinafter, this will be summarized.
In the field inversion and the line inversion, when a scanning electrode is selected to charge pixel electrodes, all the pixel electrodes are charged with the same polarity. More specifically, the potential of pixel electrodes in the corresponding line changes from a negative voltage to a positive voltage in the case of the even-numbered field, and the potential of pixel electrodes in the corresponding line changes from a positive voltage to a negative voltage in the case of the odd-numbered field. Then, the potential of a counter electrode fluctuates via the capacitance (liquid crystal capacitance also is included) between the pixel electrodes and the counter electrode (since the counter electrode has a finite sheet resistance, even if the potential is fixed at the end of a screen, the potential slightly fluctuates in the screen), the potential charged to the pixel also fluctuates due to the influence; as a result, crosstalk may occur. This also may be considered to occur since Vd appearing on both sides of (Formula 11) due to the fluctuations in the potential of a common electrode become different values between the left side and the right side, and the retention potential Vdo(±) of the pixel electrode does not become a value represented by (Formula 12).
In contrast, in the case of the column inversion and the dot inversion, when scanning electrodes in a line are selected to charge pixels, the polarity of charging is opposite between adjacent pixels. Therefore, the fluctuations in the potential of the common electrodes via the pixel electrode-common electrode capacitance cancel each other, whereby the above-mentioned crosstalk does not occur.
For the above-mentioned reasons, it is desirable to adopt the column inversion or the dot inversion.
However, in a liquid crystal display apparatus that changes the potential of a common electrode by the driving method as described in FIG. 15 with the circuit configuration in FIG. 3, the following becomes apparent: as a screen size increases, flickering and a brightness gradient (brightness inconsistency) occur conspicuously.
Furthermore, when a screen size increases, the potential of a counter electrode for writing a video signal fluctuates largely, and horizontal crosstalk becomes conspicuous. Therefore, it is required to adopt the column inversion or the dot inversion that is a driving system advantageous to horizontal crosstalk. However, in the case of adopting the driving method of FIG. 15 with the circuit configuration of FIG. 3, by controlling the potential of a common electrode at a moment when a scanning electrode is selected, a predetermined superimposed voltage with the same polarity as that of a video signal is applied to all the pixels belonging to this line to obtain the effect of an increased amplitude of the retention potential of pixel electrodes. Therefore, in the case of the driving system in which a video signal with positive and negative polarities is applied while a scanning electrode is selected as in the column inversion and the dot inversion, the effect of an increased amplitude of the retention potential of a pixel electrode cannot be obtained (more specifically, the voltage of a video signal driving circuit IC cannot be lowered). More specifically, the problems in the prior art lie in that a video display apparatus capable of lowering the voltage of the video signal driving circuit IC and reducing horizontal crosstalk cannot be achieved.